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In shown table 1 r the processor management with sets of cache as one set is controlled by cache depends upon the size and location of cache lines [8].
Therefore, any two code fragments whose addresses differ by a multiple of the cache size are mapped to the same cache line, and they cannot both be present in a direct-mapped cache simultaneously.
CB cache lines should safely fit in the cache in order to become reused efficiently.
In the case of the data cache, the burst operation is also used to write-back a modified cache line to memory.
For instance, there may be one or more cache lines in the page that are dirty in a processor's cache somewhere in the SMP.
For example, in Figure 1, considering a cache line size of two data elements, there is a reuse of Z(j, i) in the direction (0, 1, -1) which is not generated by SUIF.
We chose a commodity 300MHz Pentium II running Windows NT that has a 8KB L1 data cache, a 512KB L2 cache, and a cache line size of 32 bytes.
Assume that each element of the array a is 8 bytes, a cache line contains 32 bytes, the primary cache size is 8KB, and that memory feedback tells us that the load of a [j] suffered an 8.
The prefetching algorithm has a few compile-time parameters, which we consistently set as follows: cache line size = 16 bytes; effective cache size = 500 bytes; and prefetch latency = 300 cycles.
By making copies of all shared state, we also avoid interprocessor cache line thrashing and invalidations.
2 compliant, 33MHz, 32 bit PCI burst transfer rates of up to133MB/s; Multimode I/O cells supporting both Ultra2 (LVD) and/or legacy single-ended devices; PC99 compliant without external logic; 512 byte DMA FIFOs for more efficient PCI bus utilization: Support for FLASH for easy BIOS upgrades; Cache line streaming for improved PCI bus utilization.