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When occurs the cache line loading from dynamic RAM, the two LSB bits, are obtained from the numerator, which increments the address with four locations.
The basis of this mechanism consists in allowing multiple copies of a cache line in different slices.
For example, the Peripheral DMA controller can facilitate data transfers between the on-chip SRAM and peripherals while the processor simultaneously executes code out of its cache or does a cache line fill.
The most sophisticated of the external cache systems also offer the ability to flexibly configure the cache line size to match the size of incoming data traffic and to control the rate at which data is flushed to attached RAID systems.
Sun is also going to increase the number of transistors dedicated to L2 memory tags by a factor of eight in the Jaguar kickers while shortening the cache line size from 512 bytelines to 128 bytelines.