e500 SoC with 32 KB instruction/32 KB data L1 cache
and 512 KB L2 cache
In the private cache organization, most of the L1 cache
misses can be handled by the L2 cache, so the number of remote on-chip L2 cache accesses is reduced and it is not necessary to cross the interconnection network, which reduces the miss latency.
2 L1 Cache
miss rates for the SPARC machine (OB--miss rate for the compilation-Optimized 16 x 16 Blocked; OL--miss rate for the compilation-Optimized 16 x 16 data Laid; Imp--percentage miss rate improvement of the data laid version over the blocked version) Grid Size OB OL Imp 33 x 32 0.
40 GHz, 64 KB L1 cache
and 256 KB L2 cache per core, 30 MB L3 cache per processor, 128 GB main memory, one virtual machine using 40 virtual CPUs and the SAP MaxDB[R] 7.
Additional memory resources include 64 KB of L1 cache
and 512 KB of L2 cache.
The units also feature 64 KB L1 cache
, 1 MB L2 cache, three Ethernet interfaces up to Gb speed, and two 64-bit PMCs on independent PCI buses.
4] analyze two design alternatives for the L1 cache
of a CMP.
With its 40-bit physical address space, L1 cache
coherency and L2 cache support, the ARC HS38 processor is uniquely positioned to address the needs of these rapidly evolving high-end embedded applications, now and in the future.
It also features 32KB L1 Cache
, 256KB L2 Cache per core, 32KB On-Chip SRAM, 64-bit DDR3 memory controller with optional ECC, four10/100/1000 Ethernet ports, 2 RGMII or 4 SGMII, three USB ports with integrated PHY (2 Host and 1 OTG) lanes, two USB 2.
The SP0's processor includes an e500 System-on-Chip (SoC) integrating both an L1 cache
with 32 KB instruction and 32 KB data and a 512 KB L2 cache.