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Its tools include SystemVerilog, Verilog and VHDL analyzers and elaborators, as well as a netlist oriented object database.
Verific's products, used in various Electronic Design Automation (EDA) tools for exploring, navigating, analyzing, documenting and modifying designs, include Verilog, SystemVerilog and VHDL parsers, analyzers and elaborators, as well as a register transfer level (RTL) database.
Support of EDA standards from Interra such as Cheetah, the Verilog and System Verilog analyzer, Jaguar, the VHDL analyzer and Concorde, synthesis elaborator are used as language front-ends by several well known industry tools from major EDA vendors, such as Synopsys, Cadence, Mentor, as well as startups.
These netlist data structures are identical to those being produced by Verific's RTL elaborators, though Netlist Only Parser inputs are restricted to either Verilog or EDIF netlists.
Verific's HDL Component Software of SystemVerilog, Verilog and VHDL parsers, analyzers and elaborators has been integrated with S2C's TAI Player and is used for exploring, navigating, analyzing, documenting and modifying large designs.
The HDL Component Software from Verific includes SystemVerilog, Verilog and VHDL parsers, analyzers and elaborators.
It develops and sells C++ source code-based SystemVerilog, Verilog, VHDL and PSL/Sugar front ends -- parsers, analyzers and elaborators -- as well as a generic hierarchical netlist database for EDA applications.
Verific's HDL Component Software -- SystemVerilog, Verilog and VHDL parsers, analyzers and elaborators -- is used for exploring, navigating, analyzing, documenting and modifying large FPGA designs within the ispLEVER design environment via Lattice's new HDL Explorer[TM] capability.