p] Unrecovered strain due to permanent plastic deformation of the shape memory polymer at the end of the shape memory cycle
Its core is a 4-cycle-per-instruction 40MHz 8032 MCU -- enhanced by an internal 16-bit path that allows 2-byte instructions to be fetched in a single memory cycle
-- leading to performance averaging 9 MIPS (Million Instructions per Second) and peaking at 10 MIPS.
Its 7-stage pipeline alleviates cache memory cycle
time bottleneck, while the system bus logic repartitioning reduces the amount of logic needing to run at the maximum CPU clock speed.