subtract

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e], an eight bit reversible subtractor is required.
iv) To add/subtract the significand, a 24-bit reversible carry propagate generate adder and a 24-bit reversible subtractor is to be designed.
Thus the floating point addition/subtraction unit requires the implementation of an 8-bit reversible comparator, an 8-bit reversible subtractor, a 24-bit reversible shift register, a 24-bit reversible carry propagate generate adder, a 24-bit reversible subtractor, a 24-bit reversible comparator and a 32-bit reversible leading zero detector.
It consists of a multiplier that computes the auxiliary input sequence, a permutation block that permute the input sequence in an appropriate order and two MUXs and a adder/ subtractor used to obtain the input sequences in the necessary form as shown in equation (10).