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A fluid being used in a wafer-cleaning process behaves the same way, so as the particles become smaller and smaller, it becomes more and more difficult to achieve a sufficient flow velocity to dislodge them from the surface of the wafer.
This capability allows wafer manufacturers to reduce scrap wafers previously caused by their inability to distinguish between defect types.
Katsuhiko Miki, General Manager of the SEH Technology and Development Division, said, "Providing defect-free wafers to our customers requires greater quality control with every new chip generation, both to develop more advanced wafer manufacturing processes and to ship superior quality final products.
Tony Di Napoli, President and CEO of NexTech commented: "The deployment of the Pegasus wafer sorting tools in semiconductor fabrication facilities enables the necessary movement of semiconductor wafers in a fully automated and environmentally controlled way.
Integral Wafer is compatible with existing OEM plasma etch equipment and is currently available for plasma etch applications -- including high power dielectric etch.
Wafers are processed two at a time, loaded in a back-to-back wafer holder at the load station.
ADE will be demonstrating the WaferSight wafer flatness, shape and edge roll-off metrology system, as well as its full line of silicon wafer production and semiconductor process control systems, at Semicon West, July 11 -13, Moscone Center, South Hall, Booth 1302, in San Francisco.
ADE's full line of production metrology and inspection equipment enables high yield with low cost of ownership and a smooth transition between technology nodes for wafer suppliers, incoming quality control and semiconductor equipment manufacturers.
Reid added, "It remains our goal to be the dominant supplier of oxygen implantation equipment to the world's wafer manufacturers so they can, in turn, be the most efficient and cost-effective suppliers of SOI wafers to the semiconductor industry.
Silicon-on-Insulator (SOI) is a manufacturing technology where an insulating layer is created within a silicon wafer, isolating the top layer of silicon where the active transistors will be manufactured from the rest of the bulk silicon wafer.