In this section, we present our shadow dynamic finite state machine (SDFSM) branch prediction
technique for learning/predicting an application's unique branching patterns.
The second proposal generalizes the BPRU, improving its functionality with a twofold objective: first, that it could be used as an independent confidence estimator, and second, continuing with the application to branch inversion, that it could be used in conjunction with any correlating branch predictor in a hybrid scheme as an effective approach to increasing the original branch prediction
For the SPECint95 benchmarks, moving from perfect to realistic branch prediction
shows a performance degradation, because it reduces the number of useful instructions that are ready to issue each cycle.
We refer to this algorithm as static correlated branch prediction
is a common technique used to overcome this performance limitation imposed on high performance architectures and is the key to many techniques for enhancing ILP.
They also found a small degree of BTB and branch prediction
interference, mainly due to the positive synergy of using threads from the same application.
Like branch prediction
, value prediction also causes the execution of instructions to become speculative.
In this article, we propose a new technique for program-based branch prediction
based on a general approach that we have invented, called Evidence-based Static Prediction (ESP).
In those cases where there are not enough instructions to schedule the condition and the branch apart, the compiler uses several branch prediction
heuristics to set the prediction bit of the branch.
In these proceedings from the July 2005 conference, contributors describe their work in energy-aware computing (including speed modulation), worst-case execution time analysis (including a WCET- oriented branch prediction
system), programming languages, modeling and validation techniques including model-based and component-based approaches, operating system support, scheduling and "schedulability" analysis, quality-of-service support and wireless sensor networks (including scheduling task with Markov-chain-based constraints), multiprocessor systems, and applications of real-time computing.
Finally, we analyze how TLP stresses other hardware structures (such as the memory system and branch prediction
hardware) on an SMT.
The VIA Eden-N processor comes packed with advanced performance features such as StepAhead(TM) Advanced Branch Prediction
, sixteen pipeline stages, support for SSE multimedia instructions, a full-speed Floating Point Unit (FPU) and an efficiency-enhanced 64KB Full-Speed Exclusive L2 cache with 16-way associativity for memory optimization.