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The Section Test was administered on the fourth day of each instruction cycle.
The new F2MC-8FX series features a minimum instruction cycle three to four times faster than Fujitsu's F2MC-8L MCU series, along with a pipeline bus architecture that doubles the execution speed.
The mAgic macro-assembler optimizer uses Atmel's patent-pending code compression scheme that results in code density of only 4-bits per floating point arithmetic instruction for numerically intensive operations, and average effective code density of 50-bits per stored VLIW instruction cycle, without loss of performance.
Design-ready, tested reusable C-language source code -- Simple algorithms that act as placeholders for any of the hundreds of eXpressDSP-compliant TI third party algorithms or in-house proprietary algorithms -- Detailed memory and instruction cycle budgets -- An adaptation guide for adding algorithms, channels and drivers -- An API reference manual to document the functions of new modules -- Consistent documentation in application notes
The devices offer six I/O pins with on-chip clock oscillator, 33 single-word instructions, full-speed 1 microsecond instruction cycle at 4 MHz, seven special function hardware registers, two-level deep hardware stack, 8-bit real time clock/counter with 8-bit programmable prescaler, watchdog timer and direct LED drive.
The core can complete one or two (for DSP instructions) data memory reads and one data memory write per instruction cycle, using a rich set of addressing modes.
The ADSP2192 also delivers increased processing power through a fully transparent instruction cache that allows simultaneous mathematical operations to be performed in every instruction cycle.