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The Section Test was administered on the fourth day of each instruction cycle.
The mAgic VLIW DSP architecture is the result of 20 years of research conducted by Pier Stanislao Paolucci, mAgic architect and Permanent Researcher at the Italian National Institute of Nuclear Physics (INFN), and by key mAgic designers who participated in the Massively Parallel Processing Project (APE) VLIW architectures have massively parallel processing structures and long instruction words that allow multiple operations to be executed in a single instruction cycle.
The devices offer six I/O pins with on-chip clock oscillator, 33 single-word instructions, full-speed 1 microsecond instruction cycle at 4 MHz, seven special function hardware registers, two-level deep hardware stack, 8-bit real time clock/counter with 8-bit programmable prescaler, watchdog timer and direct LED drive.
The core can complete one or two (for DSP instructions) data memory reads and one data memory write per instruction cycle, using a rich set of addressing modes.
The PIC16C925 and PIC16C926 are available in 64-pin TQFP and 68-pin PLCC packages and offer higher clock speeds of 20 MHz and 200 ns instruction cycle, 176 to 336 bytes of RAM and either 4k x 14 words or 8k x 14 words.

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