Comm Logic Design is a member of the both the Xilinx XPERTs and the Altera ACAP programs.
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The tight integration of the Cadence(R) QPlace option and WARP global router engines in Logic Design Planner dramatically increases the first-time silicon success by bringing the required physical information into the front-end design phase.
Logic Design Planner-DSM bridges the logical and physical gap by enabling designers to accurately predict delays, routability, and die size based on a floorplan, and to fix timing problems through strong links to synthesis and timing analysis.
Logic Design Planner-DSM achieves the industry's highest level of timing prediction accuracy by providing full-featured, timing-driven placement using the QPlace quadratic placer during the logic design planning stage.
Logic Design Planner-DSM provides final QPlace placement results to the back-end routing environment, thus ensuring that front-end estimates truly correlate to the final layout implementation.
The only way to do this is to bring the same placement, clock generation, global routing, and clock generation techniques from the back-end process to the front-end through Logic Design Planner-DSM.
Logic Design Planner-DSM now uses the Cadence Timing Library Format (TLF) 3.
Logic Design Planner-DSM is available now and shipping in volume.
Moose Logic designs
, develops and maintains networking and communications systems.
Headquartered in Mississauga, Ontario, Canada, Business Logic designs
and develops a comprehensive line of Windows(R) software utilities that simplify PC maintenance for individuals and SMEs.