(redirected from Logic synthesis)
Also found in: Dictionary, Thesaurus, Medical, Encyclopedia, Wikipedia.
References in periodicals archive ?
Synplicity's tools provide outstanding performance, cost and time-to-market benefits by simplifying, improving and automating key design planning, logic synthesis, physical synthesis and verification functions for FPGA, FPGA-based ASIC verification, and DSP designers.
This comprehensive QuickLogic FPGA design environment includes fully-integrated schematic and HDL-based design entry, HDL language editors and tutorials, logic synthesis support from Mentor Graphics, 100% fully automatic place and route, static timing analysis, Verilog and VHDL functional and timing simulation support, and 3rd-party design-tool interfaces.
Synplify DSP software uniquely uses proprietary system-level synthesis algorithms to automatically generate highly optimized RTL code ready for logic synthesis, eliminating prior hand-coded, error-prone and time-consuming methodologies requiring numerous iterations between the DSP algorithm architect and the RTL hardware designer.
Synplicity's family of FPGA synthesis solutions includes the Synplify software, Synplify Pro logic synthesis software and the Synplify Premier physical synthesis software.