The expanded electrical specification for the Serial ATA physical layer (PHY
) was written to improve on first generation PHY
designs and lengthen the cable distance between transmitter and receiver.
As a result, a trend appears to be developing whereby the logic layers (Link and Transport) will go into chipsets, requiring a separate PHY
chip to connect with the logic side.
The new PHY
devices deliver high-speed, real-time data transmission and error-free reception due to their low node latency and low jitter.
We selected Mentor for the development of the USB High-Speed OTG PHY
based on our strong relationship with Mentor and Mentor's silicon-proven history of standards-compliant IP," stated Paul Ouyang, vice president of design services at SMIC.
Synopsys' DesignWare DDR PHY
compiler has helped us resolve what has traditionally been a very complex and time consuming task.
WiMedia's Certification Program is comprised of two parts, the first of which, a compliance and interoperability program, tests and "registers" Physical Layer implementations (PHYs
), based on the WiMedia Alliance's PHY
MOSAID's compiler automates the physical assembly of a DDR PHY
by leveraging MOSAID's unique "tiling" approach to PHY
construction where the individual components (tiles) of the PHY
are connected by abutment.
As a result of passing all test requirements, Staccato's Ripcord PHY
has officially been "registered" and declared ready as a foundational subcomponent of a complete WiMedia and Certified Wireless USB system.
WiQuest is the first company with a complete UWB chipset in production, the first to achieve end product FCC certification, the first to extend performance to 1 Gbps, the first with complete Windows drivers, and WiQuest has now received PHY
registration in WiMedia's first approval event," said Dr.
PARIS -- Ekinops, a leading provider of optical transport, DWDM, and aggregation solutions, today announced that Mid-Atlantic Crossroads (MAX) has deployed the Ekinops 10-Gigabit LAN PHY
(local area network physical layer device) to WAN PHY
(wide area network physical layer device) protocol converter to connect its 10-Gigabit Ethernet network to an OC-192/STM-64 submarine network between the US and Europe.
Structured ASIC Leader, and Northwest Logic offer a complete DDR/DDR2 SDRAM solution with speeds up to 667Mbps, including a DDR/DDR2 PHY
and DDR/DDR2 SDRAM Controller Cores for use on all CX6000 Structured ASIC products.
ESS Technology selected MemCore's MP4010 DDR SDRAM PHY
with Digital DLL licensed as a hard macro.