interpose

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If one probe is damaged, the entire probe receptacle can be replaced by the customer in minutes by inserting a replacement interposer set, or refurbished by the factory.
The new interposers are designed for use with the Agilent 16900 Series logic analyser providing state analysis and protocol decode at up to 1,867 mega-transfers per second (MT/s) for DDR3 DIMM applications and 1,600MT/s for SODIMM applications.
Xie, "Organic Interconnect Technology for Stacked Die Integration," Third Annual Global Interposer Technology Workshop, November 2013.
The LeCroy Mini Card interposer supports probing at speeds up to 5 GT/s (Gen2).
Abstract: This paper addresses the testing and characterization of interposer wires in a 2.5-D stacked integrated circuit, which is essential for yield learning and silicon debug.
(Huawei), have signed a Memorandum Of Understanding (MOU) to develop and advance Through Silicon Interposer (TSI) technology.
Accordingly, TSMC has applied its newest 28-nanometer process and 3D stacking technologies to produce the next-generation processor A6, which is based on the ARM architecture and will undergo TSMC's cutting-edge silicon interposer and bump on trace (BOT) methodologies.
In addition, for proposals, presentations and other professional documents, users can energize black-and-white documents with pre-printed full-color covers using the Cover Interposer.
The new SiP technology, SMAFTI(TM) (SMArt connection with Feed-Through Interposer), features a three-dimensional (3-D) chip connection whose approximately 60-micron gap and 50-micron-pitch microbump between the logic and memory devices can support transmissions up to 100 gigabits per second (Gbps).
The interposer on the top of the socket features two chip guides that help align the device with the spring probes and provide a positive lid compression stop to accurately control the spring probe deflection.
With the ever-growing demand for "More-than-Moore" solutions, Synopsys delivers design solutions for TSMC's chip-on-wafer-on-substrate (CoWoS) packaging technology enabling multiple chips side-by-side using a through-silicon-via (TSV)-driven interposer platform.
Because the chips do not have to be connected to the package through a silicon interposer with TSVs, there is nothing to potentially degrade their performance.